Odin Shen — technical articles and hands-on guides on Arm platforms

Rethinking Local LLM, Physical AI, and Edge Compute.

Every record shows exactly what was verified, so you know where you can rely on it.

41 technical articles and hands-on guides on Arm platforms by Odin Shen. How I verify my work Deep-dives

41 Articles 3 Pillars Oct 2026 Last audit

About

I'm Odin Shen, a software solutions architect focused on the Arm architecture. I work on the software layer AI needs once it moves past one-off demos — how CPUs, local-first runtimes and physical devices actually fit together. These are the posts and guides I kept along that line. Each entry covers what I actually built and verified, and is honest about what it doesn't cover yet.

Three Pillars

My work centers on three directions, each with two recommended reads.

F1

CPU-Orchestrated Runtimes

CPU and persistent runtimes as the orchestration layer of the agent era — software-defined control flow, not just execution units.

Why it mattersThe bottleneck of the agent era isn't just compute, but who orchestrates and at what standing cost — the CPU and software control layer decide scalability and affordability.

See 15 articles
F3

Physical AI

Embodied intelligence from simulation to real devices — robotics, autonomous driving, and healthy communication across distributed physical nodes.

Why it mattersEmbodied intelligence proves out in the real world — reliable communication and safety isolation from sim to deployment decide whether robots and AVs leave the demo stage.

See 15 articles

Articles

41 articles and hands-on guides, each with its verified scope spelled out so you can put it to work with confidence.

Pillar

Showing 41 / 41

B = Blog, L = Learning Path, G = Install Guide

IDTitleDomainContentReadingPillarScopeSource
B01 Using Arm Tools to Enable Machine Learning On-Device (2018) Embedded & Security Perspective 20 min F2 2 limits ↗

Using an MNIST CNN as a case study, this project combines DS-5/Streamline, C API refactoring and a SystemC/TLM accelerator model on a Cortex-A55 FVP to build an on-device ML analysis flow before physical hardware is ready. By observing instruction counts, memory access and hardware/software partitioning, it ties model execution behavior back to system-architecture decisions. Its ecosystem value is composing Arm virtual platform, performance analysis and hardware modeling into an early-stage ML/accelerator exploration baseline.

Scope of verification

  • Results come from a Cortex-A55 FVP, MNIST CNN and a SystemC/TLM accelerator model, used to observe instructions, memory behavior and architectural assumptions — not a physical-silicon benchmark.
  • Model and accelerator behavior depend on simulation parameters; timing, power, memory-system effects, driver integration and production inference performance on real hardware still require separate validation.

Topics (click to filter)

B02 Deploying Open AD Kit on Neoverse Mission-Critical & Auto Architecture 20 min F3 2 limits ↗

This project deploys an Open AD Kit / Autoware simulation in containers on an Arm Neoverse server, integrating SOAFEE, ROS 2, Docker and autonomous-driving application services. The architecture moves planning, visualization and simulation workloads into a reproducible Arm server environment so software integration can start before in-vehicle hardware is ready. Its ecosystem value is a Shift-Left baseline spanning cloud and local Arm infrastructure, supporting consistent deployment and early validation of the automotive software stack.

Scope of verification

  • The case shows that the specified Open AD Kit / Autoware services can start and reach simulation-level integration in an Arm Neoverse container environment.
  • It does not cover real ECUs, physical sensors, vehicle control, real-time deadlines, road testing or functional-safety certification, so it cannot serve as validation of a production in-vehicle system.

Topics (click to filter)

B03 Functional Safety: Containers & DDS Mission-Critical & Auto Perspective 20 min F3 2 limits ↗

Starting from software-defined vehicle architecture, this article analyzes how containers, DDS/ROS 2 communication and the safety-island pattern separate safety-critical from non-safety-critical workloads. Its core argument is to limit fault propagation through explicit service interfaces, execution boundaries and communication paths — rather than equating container isolation with functional safety. Its ecosystem value is connecting automotive safety engineering, cloud-native deployment and open middleware into a discussable architecture framework for mixed-criticality prototypes on Arm.

Scope of verification

  • The content focuses on the software-architecture relationship among containers, DDS/ROS 2 and the safety-island concept, offering interface and fault-boundary design direction; it does not specify full physical hardware validation.
  • Software isolation is not hardware-enforced separation and does not constitute an ASIL claim or ISO 26262 certification; timing interference, failure injection, the safety case and target-ECU validation must still be completed independently.

Topics (click to filter)

B04 Neoverse CSS V3 Software Bring-up Cloud & Infra Architecture 20 min F1 2 limits ↗

This project builds a pre-silicon bring-up environment for platform firmware and the OS stack on a Neoverse RD-V3 FVP, supporting software builds, full boot-flow observation and cross-component handoff debugging. The method places the SoC reference platform, firmware projects and system software into a reproducible virtual platform so integration and automation can begin before physical silicon is available. Its ecosystem value is a shared Neoverse software-development baseline across firmware, OS, tooling and silicon teams.

Scope of verification

  • The case shows the specified firmware/software stack can complete a simulated boot and component handoff on a matching RD-V3 FVP build.
  • FVP results do not cover physical-silicon timing, performance, power, I/O, memory training or hardware errata, and do not amount to production-platform qualification.

Topics (click to filter)

B05 OpenBMC & UEFI on Neoverse RD-V3 Cloud & Infra Architecture 20 min F1 2 limits ↗

This project integrates OpenBMC and UEFI on a Neoverse RD-V3 FVP, building a pre-silicon management workflow spanning BMC startup, host boot, UART, Serial over LAN and the IPMI command path. The architecture lets the BMC and host-firmware startup sequence, console access and management interfaces be observed and debugged before a physical server platform exists. Its ecosystem value is connecting open-source BMC, standard server firmware and the Arm virtual platform into a common baseline for firmware integration and CI validation.

Scope of verification

  • The implementation confirms BMC/host boot, UART, Serial over LAN and the specified IPMI interaction paths on the RD-V3 FVP; evidence is limited to virtual-platform behavior.
  • It does not validate a physical BMC, board-management I/O, power sequencing, full Redfish coverage, hardware fault handling or production server manageability.

Topics (click to filter)

B06 CPUs in AI: A Practical RAG Edge AI & Agents Perspective 20 min F1 2 limits ↗

On a DGX Spark, this project builds a local RAG pipeline, placing document cleaning, chunking, embedding, FAISS indexing and retrieval on the Grace Arm CPU while running language-model generation on the Blackwell GPU via llama.cpp. The architecture chains private-data processing, vector search and answer generation with an explicit CPU/GPU workload mapping. Its ecosystem value is concretely defining the CPU's data-processing and orchestration role in a heterogeneous AI system, and offering an understandable end-to-end RAG baseline.

Scope of verification

  • The workflow uses a specific DGX Spark, embedding/generation models, FAISS and a sample corpus to validate the full path from document processing to retrieved-context generation; it does not provide a general CPU/GPU performance comparison.
  • This workload mapping does not necessarily apply to all RAG systems; retrieval-quality evaluation, data updates, access control, observability, concurrency, high availability and production serving are not covered.

Topics (click to filter)

B07 Voice AI at the Edge Edge AI & Agents Perspective 20 min F2 2 limits ↗

On a DGX Spark, this project integrates PyAudio, WebRTC VAD, faster-whisper and vLLM into a local voice-AI pipeline spanning microphone capture, speech segmentation, transcription and text response. The Grace Arm CPU handles audio I/O, VAD and the speech-to-text workflow while the Blackwell GPU runs language-model generation, showing a heterogeneous split between voice preprocessing and generative AI. Its ecosystem value is a voice-application baseline where data stays on-device, while leaving room to swap and tune each open-source component.

Scope of verification

  • The workflow validates voice input, segmented transcript and text response under the specified DGX Spark, microphone, VAD, transcription model and vLLM configuration; output does not include TTS.
  • It provides no cross-platform latency, accuracy, noise-robustness or concurrent-session benchmarks, and does not cover wake word, speaker isolation, service reliability or production voice-interface integration.

Topics (click to filter)

B08 Robotics Reinforcement Learning on Arm Robotics & Embodied Perspective 20 min F3 2 limits ↗

On a DGX Spark, this project natively builds Isaac Sim and Isaac Lab and, using Unitree H1, RSL-RL and PPO, demonstrates a complete Arm workflow from physics simulation to humanoid policy training. The Grace Arm CPU handles software build, environment orchestration and simulation-workflow coordination, while the Blackwell GPU runs parallel physics simulation and reinforcement-learning training. Its ecosystem value is a baseline for running the Isaac robotics stack on the Grace–Blackwell heterogeneous platform, concretely showing the CPU/GPU division of labor in a robotics RL pipeline.

Scope of verification

  • The ~65k simulation steps/s figure is observed with 512 parallel environments under the specified setup; actual throughput varies with environment complexity, model, training configuration and software version.
  • The workflow focuses on simulation and policy training; results do not constitute sim-to-real transfer, physical Unitree H1 deployment, control-loop timing or robot functional-safety validation.

Topics (click to filter)

B09 Beyond the Demo: Evaluating AI Workloads on Armv9 Edge AI & Agents Perspective 20 min F1 2 limits ↗

On the CIX Armv9 platform of the Radxa Orion O6, this project deploys ERNIE MoE and MNN multimodal workloads, assessing the real-world usability of open-source AI from model execution, memory requirements, runtime behavior and application output. The two cases respectively show MoE language-model routing and text/image/audio inference, tying model capability to concrete edge use cases. Its ecosystem value is a workload-evaluation framework beyond a one-off demo, helping developers judge Armv9 deployment fit by model behavior, system constraints and application needs.

Scope of verification

  • The analysis is limited to the Radxa Orion O6, the specified ERNIE MoE and MNN multimodal models, and the article's runtime/build configuration; observations describe the deployment behavior of these two workloads.
  • It does not constitute a general Neon/SVE2 benchmark, cross-hardware performance comparison or a compatibility conclusion for all open-source models, and does not cover production serving, long-run reliability or full application integration.

Topics (click to filter)

B10 CPUs in AI: Agent Orchestration Edge AI & Agents Perspective 20 min F1 2 limits ↗

On a DGX Spark, this project integrates Hermes, Ollama and Qdrant into a persistent AI-agent runtime with event handling, state persistence, semantic memory, content retrieval and tool calling. The Grace Arm CPU owns service lifecycle, context management and workflow coordination, composing model inference, a vector database and external tools into a continuously running system. Its ecosystem value is concretely defining the CPU as the agent control plane and offering an architecture baseline extensible to on-device, long-running AI applications.

Scope of verification

  • The current implementation is a runnable MVP on a single DGX Spark, validating end-to-end integration of Hermes, Ollama and Qdrant with memory, retrieval and tool calling; it does not provide CPU utilization, model performance or cross-platform benchmarks.
  • A persistent runtime means state and services survive across interactions — not that long-run soak testing is complete. High availability, fault recovery, multi-tenant isolation, access control, service monitoring and production-grade operations still require separate design and validation.

Topics (click to filter)

B11 Rethinking Local-First AI Assistants: Always-On OpenClaw Runtime across Arm Edge AI & Agents Perspective 20 min F2 2 limits ↗

Built around OpenClaw, this project integrates Telegram, Qdrant, local document RAG, browser tools and scheduled services into a local-first agent runtime with persistent memory, deterministic routing and proactive-task capability. The architecture decouples agent workflow from the inference backend, so the same application layer can connect to vLLM/Ollama on a DGX Spark and to llama.cpp on a Radxa Orion O6 Armv9 CPU. Its ecosystem value is an agent-application baseline across Arm compute configurations that builds the local-processing / external-service data boundary into the architecture.

Scope of verification

  • The reference implementation validates that the OpenClaw workflow, persistent memory, local RAG, tool use and scheduled tasks can connect to two specified Arm-based inference environments; it provides no performance comparison between the two platforms.
  • Local-first is not fully offline — Telegram, browser search, weather and other external tools still send necessary data to external services; multi-user isolation, credential management, high availability, auditability and production security are not covered.

Topics (click to filter)

B12 From Simulation to Real Wi‑Fi: Distributed ROS 2 on Arm Robotics & Embodied Architecture 15 min F3 2 limits ↗

A ROS 2 system that runs fine on a workstation can fall apart on Wi-Fi, where bandwidth, latency and packet loss decide whether the remote side receives complete, usable sensor data. This post ties together three Learning Paths: a reproducible ROS 2 Jazzy and rmw_zenoh simulation on an Arm server, the same system distributed across containers and a Raspberry Pi, and traffic shaping with compression, access control, downsampling and QoS, compared over real Wi-Fi. Co-authored with Kwashie Andoh and Habib Ogunbanwo.

Scope of verification

  • Measurements cover the simulated workload on an Arm server and a Raspberry Pi over real Wi-Fi, comparing camera receive rate and point-cloud completeness for untuned, compression plus access control, and compression plus QoS configurations; the numbers apply only to the topics, bandwidth limits and wireless environment described.
  • The robot side is still a Gazebo simulation, not a physical robot. The policies decide which messages use the limited bandwidth but do not add Wi-Fi capacity, and the post does not cover authentication, encryption or long-run reliability.

Topics (click to filter)

L01 Multimodal VLM with MNN on Armv9 Edge AI & Agents Hands-on 15 min F2 3 limits ↗

On the Armv9 CPU of the Radxa Orion O6, this guide natively builds KleidiAI-optimized MNN, loads the pre-packaged Qwen2.5-Omni-7B-MNN model, and validates local text, image and audio inference. The workflow merges a shelf image and a spoken restock instruction into a single multimodal inference, producing a structured ticket with coverage, restock zones, quantities, deadlines and substitution policy. This CPU-first approach chains the portable MNN runtime, Armv9 optimization and a real edge application, giving developers a local multimodal baseline that needs no GPU/NPU.

Scope of verification

  • It is a CPU-only reference workflow on a single Radxa Orion O6, using the pre-packaged Qwen2.5-Omni MNN model and local assets to validate multimodal inference and structured output.
  • Hardware/software dependencies include Armv9 Linux, a native MNN/KleidiAI build, ~15 GB of model assets and at least 32 GB of free storage; actual output content and quality still depend on model, prompt and input assets.
  • Scope centers on runtime build and application-level multimodal validation; it does not cover model export, format conversion, quantization, GPU/NPU heterogeneous scheduling, cross-platform benchmarking or production integration.

Topics (click to filter)

L02 Profiling llama.cpp with Arm Streamline Cloud & Infra Hands-on 15 min F1 3 limits ↗

On an Arm Neoverse or Cortex-A platform, this guide builds KleidiAI-enabled llama.cpp, integrates Arm Streamline marker annotations and annotation channels, and captures an LLM inference timeline on the Arm CPU. The workflow splits token generation into Prefill and Decode, then observes the compute graph, tensor shapes, KleidiAI kernels and multi-threaded behavior, showing Prefill is GEMM-dominated while Decode is GEMV-dominated. This profiling method chains an open-source LLM runtime, Arm-optimized kernels and CPU-level performance data into an analysis baseline for locating bottlenecks with real execution evidence.

Scope of verification

  • It is an llama.cpp profiling reference workflow on an Arm CPU, using the specified llama.cpp b6202, KleidiAI build, Streamline annotations and gator capture to validate that Prefill, Decode, operator and multi-threaded behavior can be observed.
  • Dependencies include an Arm Neoverse or Cortex-A Linux/Android platform, Arm Performance Studio or Development Studio, a matching gator version, PMU access, and a GGUF model runnable by llama-cli.
  • Scope centers on profiling instrumentation and execution-behavior analysis; observations vary with model, prompt, llama.cpp version, build flags, thread configuration and hardware, and do not cover automatic performance optimization, cross-platform benchmarking or production workload tuning.

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L03 FunASR Speech Recognition Serving Edge AI & Agents Hands-on 15 min F1 3 limits ↗

On an Arm-based Linux server, this guide builds a ModelScope FunASR Python environment, loads pre-trained ASR and punctuation models, and validates local transcription and punctuation restoration for Chinese and English audio. The workflow chains model acquisition, audio input, speech recognition and readable text output into a minimal flow extensible to voice applications or service interfaces. This deployment baseline connects ModelScope open-source models, the FunASR toolchain and an Arm server, giving voice-AI developers an actionable local-inference starting point.

Scope of verification

  • It is a FunASR functional reference workflow on a single Arm-based Linux server, validating that pre-trained models can process the specified Chinese and English audio and produce punctuated text.
  • Dependencies include Arm64 Linux, Python, FunASR/ModelScope packages, matching model assets and decodable audio formats; results vary with model version, language, accent, recording quality and ambient noise.
  • Scope centers on model deployment and functional output; it does not cover WER/quality evaluation, streaming latency, low-latency tuning, large-scale concurrency, service reliability or production ASR operations.

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L04 OpenBMC on RD-V3 Virtual Platform Cloud & Infra Architecture 15 min F1 3 limits ↗

On an Arm Neoverse RD-V3 FVP, this guide builds OpenBMC with Yocto/BitBake and boots the BMC and host firmware alongside UEFI. The workflow validates basic boot and communication paths for the management controller and host via multiple UARTs, Serial over LAN and custom IPMI commands. This pre-silicon flow chains OpenBMC, UEFI and an Arm reference platform so firmware integration, debugging and CI validation can start before physical server hardware arrives.

Scope of verification

  • It is a pre-silicon firmware reference workflow on the RD-V3 FVP, validating OpenBMC/UEFI boot, UART, Serial over LAN and selected IPMI interactions.
  • Dependencies include a Linux build host with sufficient CPU/memory/storage, Yocto/BitBake, a matching RD-V3 software manifest, the FVP version and a long-running build environment.
  • Scope centers on boot and management-interface integration on the virtual platform; it does not cover a physical BMC, board power sequencing, full Redfish, silicon behavior, hardware fault handling or production-platform validation.

Topics (click to filter)

L05 Open AD Kit 1.0: Autoware Containers Mission-Critical & Auto Hands-on 15 min F3 3 limits ↗

On Arm Neoverse systems such as AWS EC2 or Ampere Altra, this guide launches Open AD Kit with Docker Compose, integrating the Autoware visualizer, planning and simulation services. The workflow validates that containerized services start together and produce observable autonomous-driving simulation, establishing a full path from environment deployment to application execution. This Shift-Left baseline chains SOAFEE, ROS 2, Autoware and the Arm server, helping developers rebuild a consistent in-vehicle software environment on cloud and local platforms.

Scope of verification

  • It is a containerized Open AD Kit simulation reference workflow on an Arm Neoverse server, validating deployment and basic integration of the visualizer, planning and simulation services.
  • Dependencies include a compatible Arm64 Linux server, Docker/Docker Compose, Open AD Kit container images, Autoware assets and host resources for visualization and simulation.
  • Scope centers on container startup and software simulation; it does not cover real-vehicle control, physical sensor integration, road testing, real-time behavior, fault handling or functional-safety certification.

Topics (click to filter)

L06 Open AD Kit 2.0: Safety Isolation Mission-Critical & Auto Architecture 15 min F3 3 limits ↗

Across two Arm Neoverse instances, this guide deploys an Open AD Kit simulation environment and connects safety-critical and non-safety-critical workloads via DDS/ROS 2, building a safety-island software-isolation prototype. The workflow separates services of different criticality into independent execution environments and validates an architectural approach to cross-instance communication, interface boundaries and fault isolation. This reference architecture chains ISO 26262-oriented design thinking, cloud simulation and open in-vehicle middleware, letting teams discuss and track the safety boundary before production hardware.

Scope of verification

  • It is an automotive safety-isolation reference workflow on two Arm-based Linux instances, validating software partitioning, DDS/ROS 2 communication and the safety-island architecture concept.
  • Dependencies include two interoperable Arm64 Linux environments, Open AD Kit, a matching ROS 2/DDS configuration and networking that supports cross-instance simulation and data exchange.
  • Scope centers on architecture and a software-isolation prototype; it does not cover a hardware safety island, fault injection, real-time guarantees, ASIL decomposition, ISO 26262 certification or a production in-vehicle safety case.

Topics (click to filter)

L07 ERNIE MoE on Armv9 Edge AI & Agents Hands-on 15 min F1 3 limits ↗

On the Armv9 CPU of the Radxa Orion O6, this guide deploys ERNIE-4.5 MoE with llama.cpp, validating both standard and Thinking model outputs and observing token-level expert routing. The workflow compares a baseline build with one enabling Armv9 instruction features, using pp512, tg128 and combined tests to show execution differences in prompt processing and token generation. This flow chains the open-source MoE model, llama.cpp and Armv9 optimization into an evaluation baseline that examines both model behavior and platform execution characteristics.

Scope of verification

  • It is an ERNIE-4.5 MoE deployment-and-evaluation workflow on a single Radxa Orion O6, validating model output, expert routing and execution results under the specified benchmark parameters.
  • Dependencies include Armv9 Linux, the specified llama.cpp and compiler configuration, ERNIE-4.5 model assets, sufficient memory and identical build flags, context and benchmark parameters.
  • Scope centers on the specified device, model and pp512/tg128 tests; the performance gains on the page do not apply to all Armv9 or MoE workloads, and it does not cover model quality, power, thermal behavior, long-run serving or production deployment.

Topics (click to filter)

L08 llama.cpp on DGX Spark Edge AI & Agents Hands-on 15 min F2 3 limits ↗

On the Grace–Blackwell platform of an NVIDIA DGX Spark, this guide builds both CUDA and CPU-only llama.cpp and uses a quantized GGUF model to validate GPU inference and Arm CPU execution paths. The workflow observes the Grace CPU's Armv9 SIMD usage through runtime output and instruction analysis, confirming the specified workload mainly uses Neon with no SVE/SVE2 activity. This dual-backend flow chains llama.cpp, the open-source GGUF ecosystem and the DGX Spark heterogeneous platform into a baseline for checking backend portability and CPU execution behavior.

Scope of verification

  • It is an llama.cpp backend reference workflow on a single DGX Spark, validating that CUDA and CPU-only builds run the specified quantized model and observing the CPU workload's SIMD instruction activity.
  • Dependencies include the Grace Blackwell GB10, a matching NVIDIA software stack, the llama.cpp version, CUDA/CPU build configuration, a quantized GGUF model and consistent runtime parameters.
  • Scope centers on backend execution and instruction-activity observation; the Neon/SVE results apply only to the specified workload, do not constitute a CPU–GPU hybrid benchmark, and do not cover other kernels, models, power, thermal behavior or production serving.

Topics (click to filter)

L09 DGX Spark RAG Pipeline Edge AI & Agents Hands-on 15 min F1 3 limits ↗

On an NVIDIA DGX Spark, this guide uses e5-base-v2, FAISS, Llama 3.1 8B and a llama.cpp REST server to build a local RAG pipeline from document cleaning, chunking, embedding and indexing to retrieval and generation. The workflow places document processing and vector retrieval on the Grace CPU and runs LLM generation on the Blackwell GPU, producing answers grounded in a sample corpus. This reference implementation chains Hugging Face models, open-source vector search and the Grace–Blackwell unified-memory platform into an observable end-to-end baseline for private-data RAG.

Scope of verification

  • It is a local RAG reference workflow on a single DGX Spark, using a specified corpus, embedding model, FAISS index and Llama 3.1 8B to validate the retrieval-to-generation path.
  • Dependencies include the Grace Blackwell GB10, a working llama.cpp REST server, e5-base-v2, FAISS, model and document assets, and consistent chunking, indexing and retrieval parameters.
  • Scope centers on end-to-end functional integration; it does not cover retrieval-quality evaluation, data permissions, prompt-injection defense, incremental updates, observability, HA, long-run reliability or production RAG operations.

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L10 DGX Persistent Agent: Hermes + Qdrant Edge AI & Agents Architecture 15 min F1 3 limits ↗

On an NVIDIA DGX Spark, this guide composes Hermes Agent, Ollama, Qdrant and Open WebUI with Docker into a local agent runtime with a persistent workspace, semantic memory, embeddings and contextual retrieval. The Grace CPU coordinates events, memory and service lifecycle, composing model inference, a vector database and the user interface into a full, independently swappable service path. This modular reference architecture gives developers an observable, extensible persistent-agent baseline that concretely shows the CPU's key role in local AI orchestration.

Scope of verification

  • It is a persistent-agent reference runtime on a single DGX Spark, validating that Hermes, Ollama, Qdrant and Open WebUI together provide workspace, memory, retrieval and interaction.
  • Dependencies include the Grace Blackwell GB10, Docker, matching container images, local models, embedding configuration, Qdrant storage and sufficient GPU/system memory.
  • Scope centers on a runnable MVP and its state-persistence approach; it does not cover long-run soak testing, HA, backup/recovery, multi-tenant isolation, secrets management, production security or operations SLOs.

Topics (click to filter)

L11 DGX Spark Voice Chatbot (VAD/ASR) Edge AI & Agents Hands-on 15 min F2 3 limits ↗

On an NVIDIA DGX Spark, this guide chains a USB microphone, PyAudio, WebRTC VAD, turn detection, faster-whisper and vLLM into a fully local voice-to-text-response pipeline. The Grace CPU handles audio capture, segmentation and speech-to-text while the Blackwell GPU runs LLM generation, validating segmented transcripts and text responses from live voice input. This hybrid workflow chains open-source audio processing and local LLM serving into an offline voice-application baseline where developers can tune model, segmentation and prompt strategy.

Scope of verification

  • It is an offline voice-chatbot reference workflow on a single DGX Spark, validating end-to-end integration of microphone input, VAD/turn detection, CPU speech-to-text and GPU-backed text generation.
  • Dependencies include the Grace Blackwell GB10, a USB microphone, PyAudio/WebRTC VAD, faster-whisper, vLLM, the specified models and a stable local audio environment; results vary with accent, noise and segmentation parameters.
  • Scope centers on voice input, transcription and text response, with no TTS; it also does not cover consistent latency/ASR-quality benchmarks, barge-in, far-field audio, long-run reliability or production voice-service operations.

Topics (click to filter)

L12 Windows on Arm: ArmPL Math Acceleration Cloud & Infra Hands-on 15 min F1 3 limits ↗

In a Windows 11 on Arm environment on a Lenovo ThinkPad X13s, this guide builds a native ARM64 application with Visual Studio and analyzes single-threaded, multi-threaded and Arm Performance Libraries implementations using the Spin the Cube sample. The workflow maps 3D vertex rotation onto an ArmPL BLAS routine and compares execution behavior of different implementations via FPS and CPU usage. This flow chains Windows native development, CPU profiling and Arm-optimized math libraries into a tuning baseline from baseline to library integration for compute-intensive desktop apps.

Scope of verification

  • It is a Windows on Arm optimization reference workflow on a Lenovo ThinkPad X13s, validating native ARM64 build, profiling and ArmPL BLAS integration.
  • Dependencies include Windows 11 on Arm, Visual Studio 2022, a matching Arm Performance Libraries version, the Spin the Cube sample, compiler/linker configuration and fixed workload settings.
  • Scope centers on FPS and CPU usage for a specific 3D-graphics sample; results vary with hardware, ArmPL version, compiler flags and workload, and do not cover other applications, image-quality/power analysis, cross-device benchmarking or production optimization guarantees.

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L13 Zenoh Multi-Node Pub/Sub, Storage & Query Robotics & Embodied Architecture 15 min F3 3 limits ↗

On Raspberry Pi and other Arm Linux systems, this guide builds Eclipse Zenoh from source and uses Docker to create a reproducible multi-node environment. The workflow implements pub/sub, data storage, query and queryable nodes across devices, validating real-time data exchange, historical-data retrieval and on-demand computation. This communication baseline chains Arm edge, server and cloud, giving robotics and industrial-IoT developers a distributed-data reference workflow extensible to ROS 2/DDS integration.

Scope of verification

  • It is a Zenoh multi-node reference workflow among a few Arm Linux devices, validating functional interoperability of pub/sub, storage, query and queryable patterns.
  • Dependencies include interoperable Arm Linux hosts, a Raspberry Pi or equivalent edge device, a Rust/Zenoh build environment, Docker, a matching Zenoh configuration and a reachable network.
  • Scope centers on Zenoh's functional patterns; ROS 2 appears only as an install/integration scenario and is not fully implemented as ROS 2 multi-node routing, nor does it cover latency, throughput, large node counts, weak networks, security or production-reliability benchmarking.

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L14 OpenClaw Continuum: Local-First Assistant Edge AI & Agents Architecture 15 min F2 3 limits ↗

On an NVIDIA DGX Spark and a Radxa Orion O6, this guide deploys the OpenClaw local-first assistant, integrating Telegram, local LLM inference, Ollama embeddings, Qdrant persistent memory, document RAG, browser search and scheduled tasks. The workflow connects vLLM on DGX Spark and llama.cpp on the Armv9 CPU-only platform through an OpenAI-compatible API, validating that the same application flow runs across different Arm compute configurations. The architecture decouples the inference backend from the agent workflow and clearly shows the data boundary among CPU orchestration, local data processing and external services.

Scope of verification

  • It is a single-user local-first assistant reference runtime, validating the integration of OpenClaw, memory, RAG, tools, scheduling and two Arm inference backends.
  • Dependencies include a DGX Spark or Radxa Orion O6, OpenClaw, Telegram, Qdrant, Ollama, vLLM or llama.cpp, local models, a document corpus and external search/weather services.
  • Local-first is not fully offline: Telegram, model downloads, browser search and external queries cross the local boundary; scope also excludes multi-model routing, multi-agent handoff, cross-hardware performance comparison, HA, multi-tenant isolation and production security.

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L15 Post-Quantum Crypto with PQM4 on Cortex-M4 Embedded & Security Hands-on 15 min F2 3 limits ↗

On a physical Arm Cortex-M4 board or QEMU, this guide uses pqm4 to build, test and analyze post-quantum cryptography implementations. The workflow runs test vectors, measures CPU cycles, stack usage and code size, and demonstrates integrating a new KEM scheme into pqm4, PQClean and mupq. This MCU-level evaluation baseline lets developers compare reference and Cortex-M4-optimized implementations and examine functionality, performance and memory cost with a consistent method.

Scope of verification

  • It is a PQC evaluation reference workflow on a Cortex-M4 or QEMU, validating test vectors, cycle/stack/code-size measurement and the flow for adding a new KEM implementation.
  • Dependencies include a pqm4-supported Cortex-M4 board or QEMU, the Arm embedded toolchain, pqm4/PQClean/mupq source, a matching board configuration and reproducible build settings.
  • QEMU suits functional validation but cannot represent real-hardware performance or memory behavior; the NewHope example is not a NIST-standardized algorithm, and passing tests does not cover side-channel resistance, secure-implementation review or production cryptographic certification.

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L16 Zephyr with VS Code & West Toolchain Embedded & Security Hands-on 15 min F2 3 limits ↗

In Visual Studio Code, this guide uses Ac6 Workbench for Zephyr to install host tools, import the Zephyr SDK and initialize a West workspace and board configuration. Using the NXP FRDM-MCXN947 as an example, the workflow builds, compiles, flashes and debugs the `hello_world` application while inspecting RAM, ROM and binary memory usage. This integrated flow chains the Zephyr native toolchain, VS Code and the board debug runner into a consistent baseline for Arm Cortex-M development from workspace setup to target debugging.

Scope of verification

  • It is a Zephyr development reference workflow on the NXP FRDM-MCXN947, validating workspace initialization, build, flash, debug and the memory report.
  • Dependencies include a supported development board, a Zephyr/West workspace, the Ac6 Workbench extension, the Zephyr SDK, a compatible debug probe, board definition, vendor drivers and runner configuration.
  • Scope centers on `hello_world` and toolchain bring-up; porting to other boards requires re-confirming hardware support, and it does not cover application performance, real-time behavior, power analysis, production firmware qualification or long-run hardware validation.

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L17 Zephyr Shell Subsystem & Driver Debugging Embedded & Security Hands-on 15 min F2 3 limits ↗

On the Arm Cortex-M platform of the NXP FRDM-MCXN947, this guide enables the Zephyr shell via Kconfig and builds interactive command interfaces over UART-over-USB and MQTT-over-Ethernet. The workflow uses built-in shell commands to inspect kernel, threads, network, devices and logs, validating that the same diagnostics are reachable through different transport backends. The design separates command logic from the transport layer via the Zephyr standard shell API, offering a reusable tooling baseline for firmware bring-up, testing and field diagnostics.

Scope of verification

  • It is a Zephyr shell reference workflow on the FRDM-MCXN947, validating that the UART and MQTT backends provide kernel, thread, network, device and log diagnostics.
  • Dependencies include matching Zephyr board support, UART/USB, Ethernet, sufficient memory, an MQTT broker, an IPv4 network and corresponding Kconfig/device-tree settings.
  • The MQTT example uses a local broker and a teaching setup; scope does not cover authentication, TLS, remote-command authorization, malicious-input protection, WAN deployment or production network security.

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L18 Isaac Sim Robotics on DGX Spark Robotics & Embodied Architecture 15 min F3 3 limits ↗

On an Arm-based NVIDIA DGX Spark, this guide builds Isaac Sim and Isaac Lab from source, runs Cartpole and articulated-robot simulation, and trains and evaluates a Unitree H1 humanoid locomotion policy with RSL-RL PPO. The Grace CPU handles environment coordination, reward calculation, sensor preprocessing and software build, while the Blackwell GPU runs physics, rendering, parallel simulation and policy training. This Arm64 robotics baseline chains simulation, reinforcement learning and the heterogeneous compute platform into a full path from environment validation to humanoid-policy evaluation.

Scope of verification

  • It is an Isaac Sim / Isaac Lab robotics simulation and RL reference workflow on a single DGX Spark, validating the simulation environment, RSL-RL PPO training and Unitree H1 policy evaluation.
  • Dependencies include the Grace Blackwell GB10, compatible Isaac Sim/Isaac Lab versions, RSL-RL, task configuration, GPU drivers, a Python environment and sufficient system/GPU memory.
  • Scope centers on simulation and policy training; it provides no CPU/GPU utilization, training speedup, latency or cross-platform comparison, and the policy is not deployed to a physical Unitree H1, so sim-to-real, robot safety and hardware-control validation are not covered.

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L19 Advanced Robotics RL on DGX Spark (Isaac Lab Part 2) Robotics & Embodied Architecture 15 min F3 3 limits ↗

Continuing L18's DGX Spark Isaac Sim / Isaac Lab environment, this guide trains Franka manipulation and contact-rich tasks, coordinates dual Shadow Hands with MAPPO/IPPO, and builds a humanoid motion policy via AMP. The workflow places RSL-RL, RL Games, skrl and Stable Baselines3 into the same Arm64 simulation environment, validating how different tasks, algorithms and checkpoints are used. This advanced baseline helps robotics developers choose an RL framework by task registration, algorithm support and checkpoint compatibility — rather than assuming a single library fits all tasks.

Scope of verification

  • It is an advanced Isaac Lab reference workflow on top of L18, validating that Franka, dual Shadow Hands and humanoid AMP tasks can be trained and replayed in the specified DGX Spark simulation stack.
  • Dependencies include a completed, version-compatible L18 environment, Isaac Sim/Isaac Lab, each RL library, task configurations, training parameters and matching checkpoints.
  • Scope qualitatively confirms simulation visuals and training behavior; it provides no unified convergence, sample-efficiency or library performance comparison, and the policy is not validated on physical Franka, Shadow Hand or humanoid hardware.

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L20 Build a ROS 2 + Zenoh Simulation on an Arm Server (Part 1) Robotics & Embodied Architecture 15 min F3 3 limits ↗

On an Arm server, this guide uses Docker to set up a ROS 2 Jazzy and `rmw_zenoh` environment running Neobotix ROX, Gazebo, Navigation2 and RViz simulation. The workflow validates the ROS graph, navigation, sensor data, Zenoh router discovery and shared-memory transport, comparing loopback and shared-memory latency with a specified point-cloud workload. This Arm64 robotics-middleware baseline gives developers an observable single-machine simulation environment and a starting point for later distributed deployment across server, container and Raspberry Pi.

Scope of verification

  • It is a containerized ROS 2/Zenoh simulation reference workflow on a single Arm server, validating the navigation stack, ROS graph, sensor topics, router discovery and shared-memory transport.
  • Dependencies include an Arm64 Linux server, Docker, ROS 2 Jazzy, `rmw_zenoh`, the Neobotix ROX simulation, Gazebo, Navigation2, RViz and a consistent container/network configuration.
  • Scope excludes physical robots, cross-device networking and wireless impairment; the ~30% shared-memory latency improvement applies only to the specified reference system and point-cloud workload and does not generalize to all ROS 2/Zenoh workloads.

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L21 Distributed ROS 2 + Zenoh (Part 2) Robotics & Embodied Architecture 15 min F3 3 limits ↗

Extending L20's single-machine simulation, this guide deploys a ROS 2/Zenoh distributed system across an Arm server, a remote-control container and a Raspberry Pi, connecting nodes in router/client mode. The workflow validates remote RViz, ROS-graph discovery, `/scan` sensor rate and bidirectional talker/listener, and compares the isolation behavior of ROS namespaces, `ROS_DOMAIN_ID` and Zenoh namespaces. This cloud-to-edge baseline uses shared Arm64 ROS 2 packages to build a distributed robotics topology without cross-compilation, giving multi-robot deployment an observable integration starting point.

Scope of verification

  • It is a distributed ROS 2/Zenoh reference workflow within one reachable network, validating discovery, sensor data and bidirectional messaging among a single Arm server, a remote-control container and a Raspberry Pi.
  • Dependencies include a completed L20 environment, Arm64 ROS 2/Zenoh packages, a Raspberry Pi, matching router/client configuration, namespace settings and an interoperable network.
  • Scope centers on a few nodes and a simulated robot; the second-edge-device collision/isolation experiment is optional, and it does not cover fleet scale, WAN latency, network recovery, encryption, long-run reliability or production security.

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L22 Tune Zenoh Performance over Wireless Networks (Part 3) Robotics & Embodied Architecture 15 min F3 3 limits ↗

Continuing the ROS 2/Zenoh system of L20–L21, this guide establishes a comparable wireless-network baseline using fixed measurement of `/scan`, camera image, point cloud and link traffic. The workflow first simulates bandwidth, latency, jitter and packet loss with `tc`/`netem`, then evaluates, item by item on a Raspberry Pi 2.4 GHz Wi-Fi, how compression, downsampling, access control and QoS affect rate, bandwidth and regularity. This evidence-driven tuning process helps robotics developers make traceable transport-policy choices based on message importance, integrity and limited bandwidth.

Scope of verification

  • It is a Zenoh wireless-tuning reference workflow on the specified Arm server, Raspberry Pi and simulated sensor workload, validating the observable impact of network impairment and multiple traffic policies.
  • Dependencies include the L20/L21 environment, 2.4 GHz Wi-Fi, `tc`/`netem`, fixed `/scan`/image/point-cloud traffic, identical Zenoh configuration and a repeatable measurement procedure.
  • Results vary with signal, interference, access point, hardware and message size; `tc`/`netem` can only simulate part of the network constraints, and access control is not authentication or encryption, so general optimal settings or production security are not covered.

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L23 Neoverse RD-V3 Software Stack Bring-up Cloud & Infra Architecture 15 min F1 3 limits ↗

On an AWS m7g.4xlarge Ubuntu host, this guide uses a pinned manifest and a containerized build environment to build Neoverse RD-V3's TF-A, RSE, SCP/MCP, UEFI, GRUB, Linux kernel and Buildroot. The workflow observes multiple UARTs on a matching RD-V3 FVP, validates the full boot chain and Linux login, and extends to platform-control firmware modification and RD-V3-R1 dual-chip simulation. This pre-silicon baseline chains several upstream firmware projects and the Arm FVP, letting platform developers reproduce, trace and debug software handoff before silicon is available.

Scope of verification

  • It is a pre-silicon software-stack reference workflow on the RD-V3/RD-V3-R1 FVP, validating pinned firmware components, multi-UART boot, Linux login, firmware modification and dual-chip simulation.
  • Dependencies include an AWS m7g.4xlarge or equivalent Arm build host, Ubuntu 22.04, a containerized toolchain, a matching manifest release, the FVP version, sufficient storage/memory and long-running build capacity.
  • Scope shows the specified software stack can complete boot and firmware handoff on the FVP; it does not cover physical-silicon timing, performance, power, I/O, memory training, hardware errata, secure-boot certification or production-platform validation.

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L24 Run the AV1 and VP9 codecs on Arm Linux Cloud & Infra Hands-on 15 min F1 3 limits ↗

On an Arm Linux server, this guide builds `libaom` and `libvpx` from source, runs unit tests, and uses fixed videos to test AV1/VP9 encoding. The workflow compares frame rate across resolution, bit depth, on-demand/real-time mode and `--cpu-used` settings, showing the trade-off between encoding speed and output quality/compression. This codec-evaluation baseline chains Neon/SVE2-optimized open-source libraries and the Arm CPU into a repeatable video-workload build, test and tuning path.

Scope of verification

  • It is an AV1/VP9 codec reference workflow on an Arm Linux server, validating `libaom`/`libvpx` build, unit tests and encoding output for fixed sample videos.
  • Dependencies include Arm64 Linux, compiler/build tools, specified `libaom`/`libvpx` source revisions, test data and consistent resolution, bit depth, threading, mode and `--cpu-used` settings.
  • The examples do not record full hardware/system configuration and cannot be used for cross-CPU or cross-cloud-instance performance comparison; `--cpu-used` trades speed against quality/compression, so full evaluation still requires fixed input and comparison of quality, bitrate, power and long-run behavior.

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L25 Migrate-Ease: Porting x86 to Arm Cloud & Infra Hands-on 15 min F1 3 limits ↗

On Arm64 Linux, this guide uses the read-only `migrate-ease` tool to analyze a local source tree or a specified Git repository/branch, scanning C/C++, Go, Python, Rust, Java and Dockerfiles. The workflow detects x86-specific assembly, intrinsics, compiler flags, build logic and dependencies that lack AArch64 support, emitting a JSON report or Web UI for item-by-item review. This static-analysis baseline moves the x86-to-Arm compatibility check ahead of the build, giving migration planning and remediation prioritization a repeatable evidence entry point.

Scope of verification

  • It is a source-level migration-assessment reference workflow, validating that `migrate-ease` can read-only scan a local/Git codebase and emit architecture-compatibility findings.
  • Dependencies include an Arm64 Linux host, `migrate-ease`, a readable source tree or Git repository/branch, and full access to the scanned languages, build files and dependencies.
  • The tool scans files in the source tree without judging whether they actually participate in the build, so false positives or missed runtime issues are possible; a passing report does not mean the application has successfully built, run correctly or met expected performance — Arm-native build, test and benchmark are still required.

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L26 Signed FIT U-Boot Secure Boot on Cortex-A Embedded & Security Architecture 15 min F2 3 limits ↗

On a QEMU Arm `virt` machine or a TI AM62L EVM, this guide builds Zephyr and U-Boot and packages the Zephyr binary into a FIT image signed with SHA-256/RSA-2048. The workflow embeds the trusted public key into the U-Boot control device tree and uses wrong-key and tampered-image tests to validate that the boot command rejects payloads failing the signature check. This flow chains FIT, U-Boot, device tree and Zephyr into a payload-verification baseline for Cortex-A developers moving from virtual platform to physical board.

Scope of verification

  • It is a signed-FIT reference workflow on a QEMU Cortex-A53 or TI AM62L EVM, validating U-Boot's signature acceptance and rejection paths for the Zephyr payload.
  • Dependencies include QEMU Arm `virt` or the AM62L EVM, Zephyr/U-Boot source, a cross toolchain, OpenSSL key material, FIT/device-tree configuration and matching boot media and board setup.
  • The flow only covers U-Boot verifying the Zephyr payload; QEMU has no boot-ROM/eFuse root of trust and the AM62L remains in HS-FS development state. Production deployment still needs earlier-stage signing, private-key protection, console/environment lockdown, vendor key provisioning and HS-SE lifecycle transition.

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L27 ROS 2 Device Connect Robotics & Embodied Hands-on 15 min F3 3 limits ↗

On Arm Linux, this guide uses the Device Connect adapter to wrap an existing containerized ROS 2 system into a typed device discoverable and callable by a peer device or AI agent. The workflow exposes read-only inspection RPCs for nodes, topics, services, packages, interfaces and topic metadata via `docker exec`, and extends through profiles to a Raspberry Pi 5 camera and a robot driver with allowlisted actions, bounded velocity and explicit stop. This integration pattern keeps ROS 2 as the robot's internal graph while adding an external capability layer controlled by the device owner, so external tools need not handle ROS 2 topics, QoS or container configuration directly.

Scope of verification

  • It is a ROS 2/Device Connect reference workflow on Arm Linux, validating containerized ROS 2 inspection, device discovery, typed RPC and the controlled extension of camera/robot profiles.
  • Dependencies include Arm64 Linux, Docker, a ROS 2 container, Device Connect edge/agent packages, the `ros2-device-connect` adapter, a Zenoh D2D network and a matching profile/allowlist configuration.
  • The tutorial runs with `DEVICE_CONNECT_ALLOW_INSECURE=true` on a trusted local network with no transport authentication; the adapter provides no arbitrary ROS 2 passthrough, and allowlists, velocity bounds and stop commands do not replace authentication, authorization, a physical safety controller or an emergency-stop system.

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G01 Install Cyclone DDS Robotics & Embodied Hands-on 5 min F3 1 limit ↗

On AArch64 Linux, this guide builds and installs Eclipse Cyclone DDS from source, enables examples and tests, and validates basic discovery and pub/sub data exchange with `HelloworldPublisher` and `HelloworldSubscriber`. Its ecosystem value is a reproducible minimal DDS-middleware install baseline on Arm, letting ROS 2, robotics and industrial-IoT developers first confirm core communication before extending to real applications and network topologies.

Scope of verification

  • The Hello World test only confirms basic discovery and message exchange on the same Arm Linux host; it does not validate cross-host, container, Wi-Fi, multicast, QoS, security, latency, throughput or long-run reliability. The guide also does not pin a Cyclone DDS release or commit; for a reproducible production environment, lock the version and complete network, QoS and security setup per the official docs.

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G02 Install ROS 2 Robotics & Embodied Hands-on 5 min F3 1 limit ↗

On AArch64 Ubuntu, this guide installs the matching ROS 2 LTS release for the OS version, configures the package source, developer tools, `rosdep` and the shell environment, and validates basic topic publish-subscribe with a C++ talker/listener example. Its ecosystem value is a minimal runnable starting point for an Arm robotics development environment, letting developers confirm the native ROS 2 toolchain works before connecting sensors, controllers, simulation or multi-node systems.

Scope of verification

  • The talker/listener test only confirms basic ROS 2 node and topic communication on one host; it does not validate cross-device discovery, DDS/RMW configuration, QoS, real-time behavior, network stability, hardware drivers or production deployment. Install commands pair Ubuntu with the ROS 2 release; package availability, support windows and repository status should follow the official ROS 2 docs.

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How I verify

Self-audited · Oct 2026. “Audit” here means the author re-verified each asset's scope, validation platform and boundaries — not third-party certification.

No unverified production claims. “Reproducible” means following the page's steps yields the expected output; nothing is called a production service before long-run soak testing.

No generalized benchmark claims. Any ratios or performance figures apply only to the specific configuration, not a general benchmark.

Canonical source. Each asset's canonical source is its official Arm page; this site provides guided summaries and boundary notes.